Title :
Computing optimal clock schedules
Author :
Szymanski, Thomas G.
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Abstract :
The author considers the problem of optimizing the parameters of a multiphase clock for a circuit containing both edge-triggered flip-flops and level-sensitive latches. He demonstrates that recently proposed linear programming (LP) approaches to this problem require excessive computation time. An alternative method is proposed in which LP constraints are generated selectively, thus allowing fast solution. Various formulations of short path constraints are discussed, as are experimental results for large circuits
Keywords :
flip-flops; linear programming; logic CAD; logic circuits; edge-triggered flip-flops; level-sensitive latches; linear programming; multiphase clock; optimal clock schedules; short path constraints; Clocks; Combinational circuits; Delay; Flip-flops; Integrated circuit interconnections; Latches; Linear programming; Multidimensional systems; Processor scheduling; Timing;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227771
