An efficient design & verification workflow for evaluating the proper operation of clock and data recovery systems

This paper describes a design and verification workflow aimed at ensuring the convergence and proper operation of CDR systems, in a small number of simulation runs. A fabricated 6-Gbps half-rate binary CDR is analyzed in order to demonstrate the consistency between the verification and test results. This particular system had symptoms of unusual jitter generation. A combination of Verilog-A modeling, MATLAB, and SpectreS tools were used in order to extract and verify the measured results in simulation. The convergence, locking time, and stability can be obtained using the proposed methodology in a relatively short period of time. The corroborating test and verification results confirmed the source of the jitter generation problem in the system under study. Related design and performance issues are also discussed