Hardware implementation of block matching algorithm with FPGA technology

In MPEG and VCEG standards, motion estimation is used to eliminate the temporal redundancy. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a reconfigurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present the design of a motion estimation circuit and its hardware implementation on FPGA based on "full search block matching" algorithm according to H.263 standard. We specified, simulated, and synthesized SAD\´s engine with VHDL description. The proposed design is implemented on a "stratix" FPGA using EPIS10B672C6 component. Our simulations confirm the functionality of the algorithm using "ModelSim" simulator and synthesis using the "Quartus" software provided by ALTERA. This study represents a mean stone for FPGA implementation of motion estimation algorithms.