Power islands: a high-level synthesis technique for reducing spurious switching activity and leakage

This work introduces a high-level synthesis (HLS) methodology that eliminates the spurious switching activity (SSA) and the leakage in a great portion of the resulting circuit through the use of power islands. A power island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all of the logic contained within it is idling. By powering down an island: (1) the spurious switching that results from the broadcast to idle components is silenced and (2) the power consumption due to leakage in inactive components are eliminated. Our experiments conducted on several synthesis benchmarks using a transistor-level simulator showed an average reduction of 11% in total power consumption due to the power islands without introducing any overhead. We can project that in future technologies, when leakage becomes a more dominant component of the overall power, significantly more savings can be gained from design with power islands