DocumentCode :
3257606
Title :
Hcompare: a hierarchical netlist comparison program
Author :
Batra, Pradeep ; Cooke, David
Author_Institution :
Sun MicroSystems, Mountain View, CA, USA
fYear :
1992
fDate :
8-12 Jun 1992
Firstpage :
299
Lastpage :
304
Abstract :
The authors present Hcompare, a hierarchical comparison tool. This tool does a true hierarchical comparison with the user-defined hierarchies. Errors are reported hierarchically in terms of user-defined blocks. Error reports are easy to read as errors are reported in terms of mismatched connections to design blocks. Run time is on the order of minutes even for large blocks with 2-3 million devices. Input to the tool is in the form of two netlists: one from the definition, typically schematic, and one from implementation, typically layout. The program has been used to compare layout vs schematic netlists for two chips with over two million devices each
Keywords :
VLSI; circuit layout CAD; Hcompare; VLSI; hierarchical netlist comparison program; layout; user-defined blocks; Design automation; Error correction; Integrated circuit layout; Logic design; Logic devices; Silicon; Sun;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
ISSN :
0738-100X
Print_ISBN :
0-8186-2822-7
Type :
conf
DOI :
10.1109/DAC.1992.227789
Filename :
227789
Link To Document :
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