Title :
K-ary n-cube based off-chip communications architecture for high-speed packet processors
Author :
Engel, Jacob ; Kocak, Taskin
Author_Institution :
Dept. of Electr. & Comput. Eng., Central Florida Univ., Orlando, FL
Abstract :
A k-ary n-cube interconnect architecture is proposed, as an off-chip communications architecture for line cards, to increase the throughput of the currently used memory system. The k-ary n-cube architecture allows multiple packet processing elements on a line card to access multiple memory modules. The main advantage of the proposed architecture is that it can sustain current line rates and higher while distributing the load among multiple memories. Moreover, the proposed interconnect can scale to adopt more memories and/or processors and as a result increasing the line card processing power. Our results portray that k-ary n-cube sustained higher incoming traffic load while keeping latency lower than its shared-bus competitor
Keywords :
integrated circuit interconnections; microprocessor chips; packet switching; system buses; high-speed packet processors; k-ary n-cube interconnect; line cards; memory system; multiple packet processing; off-chip communications; Bandwidth; Computer architecture; Delay; Electronic mail; Jacobian matrices; Memory management; Power system interconnection; Routing; Telecommunication traffic; Throughput;
Conference_Titel :
Circuits and Systems, 2005. 48th Midwest Symposium on
Conference_Location :
Covington, KY
Print_ISBN :
0-7803-9197-7
DOI :
10.1109/MWSCAS.2005.1594497