Learning on VLSI: a general purpose digital neurochip

Summary form only given. A general-purpose digital neurochip for the resolution and the learning stages of neural algorithms is presented. It updates neuron states and synaptic coefficients in parallel on input neurons. Using 1.6- mu m CMOS technology, a chip can implement 32 input and 16 output neurons with 16-bit synaptic coefficients. Typical on-chip operation time is 2 mu s. Many circuits can be assembled to simulate structured or large-size nets as well as higher order nets. By choosing adapted parameters, most of the learning rules considered so far for neural networks can be programmed. In particular, the error backpropagation algorithm is implemented by a simple arrangement of chips with optimal use of the chip parallelism and minimal interchip communications. Specification of the required precision for synaptic weights is given by theoretical arguments and numerical simulations: 16 bits per synapse should be sufficient for almost all the cases considered.<>