• DocumentCode
    3257738
  • Title

    Plane parallel A* maze router and its application to FPGAs

  • Author

    Palczewski, Mikael

  • Author_Institution
    XILINX, San Jose, CA, USA
  • fYear
    1992
  • fDate
    8-12 Jun 1992
  • Firstpage
    691
  • Lastpage
    697
  • Abstract
    A plane-parallel maze-routing method for field programmable gate arrays is presented. It was demonstrated that a plane-parallel approach was significantly faster than traditional approaches, without compromising quality as measured by routing length. A framework is established for unified code to support traditional wire routing, timing driven routing, and plane parallel and global routing
  • Keywords
    circuit layout CAD; logic arrays; network routing; field programmable gate arrays; global routing; plane parallel; plane-parallel; plane-parallel maze-routing method; routing length; timing driven routing; Field programmable gate arrays; Joining processes; Length measurement; Logic; Pins; Routing; Switches; Timing; Velocity measurement; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-2822-7
  • Type

    conf

  • DOI
    10.1109/DAC.1992.227797
  • Filename
    227797
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3257738