A low power low voltage gain controllable sigma-delta modulator

A switch-capacitor SDM with a controllable gain design at the signal input stage has been proposed. This gain control is realized by increasing the input sampling capacitors to obtain a higher signal gain of the first integrator. This method can greatly reduce the switch-capacitor thermal noise due to the input sampling capacitors without degrading the SDM noise shaping feature. The adaptive gain control can be achieved by tracking the input signal strength. The design consumes 24 ¿W from a 1 V supply. It was fabricated in a 0.18 ¿m CMOS technology. The modulator´s SNDR for a 5 mV_p-p small input signal increases from 26 dB to 33 dB with a gain factor of 4, and the ENOB of the gain controlled SDM is also improved from 10 bit to 11 bit.