An ASIC methodology for the design of DSP standard products

An approach that has been used successfully in the design of a family of high-performance digital signal processing (DSP) standard products is described. It offers the advantage of a short design cycle without sacrificing performance. The methodology relies on the availability of a well characterized standard-cell library, an accurate gate-level simulator, a behavioral simulator for architectural evaluations, and module generators for generic DSP operators such as multipliers and adders. The methodology has the flexibility to retarget the logic or structural description into a physical implementation that can be either array-based, cell-based, or full custom. Two design case studies of 20-MHz DSP standard product chips are described