Control optimization in high-level synthesis using behavioral don´t cares

The authors present techniques for optimization of the control part of designs generated by high-level synthesis. The concept of behavioral don´t cares is defined and algorithms for extracting behavioural don´t care conditions from a high-level description are given. These don´t care conditions are used for the optimization of the control logic and the finite-state machine, after high-level synthesis. It is shown that the use of behavioral don´t cares combined with finite automata state minimization algorithms can further optimize the logic and reduce the number of states, after scheduling and allocation. Results from several benchmark examples showed that significant area and delay reductions can be obtained with these techniques