Distributed design-space exploration for high-level synthesis systems

Author

Dutta, Rajiv ; Roy, Jayanta ; Vemuri, Ranga

Author_Institution

Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA

fYear

1992

fDate

8-12 Jun 1992

Firstpage

644

Lastpage

650

Abstract

A parallel algorithm for design-space exploration and trade-off analysis is presented. Coarse-grained parallelism is introduced by generating multiple module bags and performing scheduling and performance analysis of the data flow graph for each module bag in parallel. This algorithm was implemented on a multiple processor machine as part of a distributed high-level synthesis system. Experimental results showed reduction in search time, improvement in design quality, and close-to-linear speedup

Keywords

digital integrated circuits; logic CAD; parallel algorithms; performance evaluation; scheduling; data flow graph; design quality; design-space exploration; distributed high-level synthesis system; high-level synthesis; module bag selection; multiple module bags; multiple processor machine; parallel algorithm; performance analysis; scheduling; search time; trade-off analysis; Algorithm design and analysis; Clocks; Cost function; Flow graphs; High level synthesis; Libraries; Monitoring; Parallel processing; Processor scheduling; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE

Conference_Location

Anaheim, CA

ISSN

0738-100X

Print_ISBN

0-8186-2822-7

Type

conf

DOI

10.1109/DAC.1992.227806

Filename

227806