Title :
The automatic generation of bus-interface models
Author :
Leong, Yew-Hong ; Birmingham, William P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
The authors describe a system, HIDE, that automatically creates very high-speed IC description language (VHDL) bus-interface models from timing and bus-state diagrams. The information required by HIDE is easily found in component documentation. Thus, HIDE reduces the time for understanding a component´s operation and for writing the model. An Intel iAPX80386 model was developed in less than one week. HIDE can also be used to develop executable specifications, as its inputs are a normal element of the IC design process
Keywords :
circuit CAD; formal verification; specification languages; 80386 bus-interface; HIDE; IC design process; Intel iAPX80386 model; VHDL; bus-interface models; bus-state diagrams; component documentation; executable specifications; high-speed IC description language; timing diagrams; Automatic control; Automation; Computer science; Digital systems; Documentation; Hardware design languages; Process design; Timing; Very large scale integration; Writing;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227808
