State assignment using input/output functions

A finite state machine synthesis procedure is proposed. The aim of the synthesis procedure is to combine some state variable functions with primary inputs and primary output functions, the former requiring zero area and the latter having to be implemented. The number of next state functions that have to be implemented is thus reduced, potentially reducing the area of the synthesized circuit. Also, as more of the state variables are directly observable and controllable, the testability of the implementation is increased. Experimental results are given to demonstrate the effectiveness of the procedure proposed in reducing area