Signal gain optimization in metal-insulator-silicon optical detector

A CMOS optical detector with a metal-insulator-silicon (MIS) structure is considered. A two-level voltage bias provides a transient between two quasi-equilibrium inversion modes. The simple readout procedure provides the reading of the integrated information with a significant current gain, which is about 10⁴ for high external loads (>10 KΩ). In this paper, the case of small loads is considered (∼100 Ω). Simulations show that the resistance of the silicon base changes drastically due to a double injection of carriers in the base. The current gain obtained experimentally reaches the value of 10⁶ at low loads. Dependencies of integration and readout currents on time allow also a determination of the generation and recombination lifetimes of minority carriers.