Title :
Solving the state assignment problem for signal transition graphs
Author :
Lavagno, Luciano ; Moon, Cho W. ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The authors propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit. They first solve the STG state assignment problem by minimizing the number of states in the corresponding finite-state machine (FSM) and by using a critical race-free state assignment technique. State signal transitions may be added to the original STG. A lower bound on the number of signals necessary to implement the STG is given. The technique significantly increases the applicability of STGs for specifying asynchronous circuits
Keywords :
graph theory; logic design; STG state assignment; signal transition graph; state assignment problem; Asynchronous circuits; Automata; Clocks; Delay; Design automation; Hazards; Minimization; Moon; Process design; Wire;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227821