Hierarchical test generation under intensive global functional constraints

The authors address the system-level functional constraint problem for hierarchical test generation. They propose several approaches to solve both control constraints and bus constraints. For control constraints, circuit behavior information is exploited to derive valid control Boolean covers for different modules. For bus constraints, a constant value bus constraint abstraction technique and a test cube justification technique are introduced. These proposed algorithms have been implemented in the hierarchical test generation package, ARTEST, and four high-level circuits with different constraint characteristics have been tested in experiments. The experimental results show the effectiveness of combining the control cover abstraction technique and the test cube justification technique as a complete solution to the global functional constraint problem