Title :
Partitioning by regularity extraction
Author :
Rao, D. Sreenivasa ; Kurdahi, Fadi J.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Abstract :
The authors present a general methodology for extracting regularity at any level of hierarchy, and explore the problem of digital system partitioning by extraction of regularity. They consider system-level partitioning to demonstrate that regularity can lead to reduced design costs. The digital system is modeled with cyclic directed graphs. A prototype system based on these ideas has been built. Some examples are discussed
Keywords :
circuit layout CAD; directed graphs; cyclic directed graphs; digital system partitioning; general methodology; prototype system; regularity extraction; system-level partitioning; Circuit testing; Cost function; Design automation; Digital systems; Hardware; Power generation economics; Prototypes; System testing; Systolic arrays; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227830
