High-level synthesis from VHDL with exact timing constraints

The authors present a solution to the interface timing problem in high-level synthesis by requiring that the algorithmic specification must completely determine the interface timing on the basis of cycles. They explain the timing problem and discuss the solution, which is closely related to a specific subset of the very high-speed IC description language (VHDL). This approach has been integrated into the high-level synthesis system CALLAS. An overview is given of the synthesis techniques of CALLAS. Controller reduction, which is the key transformation for satisfying the timing constraints, is discussed. The algorithms are formally described. The timing concept is compared to other approaches. Experimental results are provided