Title :
Equivalence of robust delay-fault and single stuck-fault test generation
Author :
Saldanha, Alexander ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
A link between the problems of robust delay-fault and single stuck-fault test generation is established. In particular, it is proved that all the robust test vector pairs for any path delay-fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network. Since single stuck-fault test generation is a well solved problem, this result yields an efficient algorithm for robust delay-fault test generation. Experimental results demonstrate the efficiency of the proposed technique
Keywords :
delays; fault location; logic testing; equivalence; robust delay-fault; robust test vector pairs; single stuck-fault test generation; Calculus; Circuit faults; Circuit testing; Clocks; Delay; Logic circuits; Logic testing; Proposals; Robustness; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-2822-7
DOI :
10.1109/DAC.1992.227841
