Delay fault test generation for scan/hold circuits using Boolean expressions

A new test generation technique for path delay faults in scan/hold type circuits is presented. It uses reduced ordered binary decision diagrams to represent Boolean functions implemented by the subcircuits in a circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit under test and a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated for each fault. These constraints are then manipulated to obtain robust tests, if they exist; otherwise, nonrobust tests are obtained from the constraint functions, if they exist. An implementation of this technique was used to analyze delay fault testability of several ISCAS ´89 benchmark circuits