High speed implementation of Serpent algorithm

In this paper, we report our implementation of Serpent algorithm on Virtex XCV1000 FPGA using partial evaluation technique. Partial reconfiguration is used in this implementation. The major effect of using partial reconfiguration is higher performance and reduced required area compared with other implementations. The design is pipelined in inner-outer of each round of the cipher and the results show that this implementation has higher performance in terms of encryption/decryption speed compared with other recently reported implementations. Our design was described with VHDL. The JBits software was used to do partial reconfiguration.