High speed implementation of Serpent algorithm

Author

Najafi, B. ; Sadeghian, B. ; Zamani, M. Saheb ; Valizadeh, A.

Author_Institution

Dept. of Comput. Eng. & IT, Amirkabir Univ. of Technol., Tehran, Iran

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

718

Lastpage

721

Abstract

In this paper, we report our implementation of Serpent algorithm on Virtex XCV1000 FPGA using partial evaluation technique. Partial reconfiguration is used in this implementation. The major effect of using partial reconfiguration is higher performance and reduced required area compared with other implementations. The design is pipelined in inner-outer of each round of the cipher and the results show that this implementation has higher performance in terms of encryption/decryption speed compared with other recently reported implementations. Our design was described with VHDL. The JBits software was used to do partial reconfiguration.

Keywords

cryptography; field programmable gate arrays; hardware description languages; high-speed integrated circuits; pipeline processing; reconfigurable architectures; JBits software; Serpent algorithm; VHDL; Virtex XCV1000 FPGA; encryption-decryption speed; partial evaluation technique; partial reconfiguration; Algorithm design and analysis; Application software; Application specific integrated circuits; Cryptography; Equations; Field programmable gate arrays; Hardware; NIST; Software algorithms; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Print_ISBN

0-7803-8656-6

Type

conf

DOI

10.1109/ICM.2004.1434767

Filename

1434767