Rhythmic codebook of 300mV precharge, 1ns, low power SRAM in vector quantizers

The effective design of semiconductor memory pertaining to the power consumption, speed and area penalty has always been the crucial task in embedded computing applications. The work presented in this paper is exact and innovative mathematical model based implementation of 32 kb SRAM optimized for power and speed. The model has been developed for a cell, array, and pre-charge, I/Os and periphery devices for their exact behavior and then effective design is obtained by running the model through computing engine. The supply and pre-charge to an array of SRAM are swept and optimized combination is found out for minimum power dissipation and highest achievable access time. The SRAM array rows are controlled by the Gating Transistor Power Saving Technique (GTPST). Redundant columns have been found to make the memory fault tolerant. Similarly the the bitline passive leakage sensing and compensation scheme also has been presented. The experimental result shows 0.25 ¿W dissipation at V_DD of 620 mV and pre-charge of 300 mV. The minimum attainable bit line swing is 200 ¿V/ns at V_DD of 620 mV and precharge of 500 mV, both of which are state-of-art of its kind. The power saving of 13% is reported. The design by mathematical model, schematic and layout of 32 Kb memory chip and simulation are carried out for development of codebook memory that finds application in embedded signal processing.