Hierarchical physical design system

The physical design system aims at high density and short turnaround time. Hierarchical methods divide the entire design logically into chips, and chips into partitions of manageable sizes. As the chips are placed on a chip carrier, the wire lengths of all chip interconnections are kept to a minimum. In parallel, chip I/Os are assigned to reflect routing on the chip carrier. This preassignment of chip-I/Os takes into account when partitions are placed on the chip. The partitions and their circuits are placed on the chip on a periodic array of sites, as is done for gate arrays, but, as for custom chips, with the highest possible density. All partitions contain not only the circuitry and internal wiring but also all connections that enter, leave, and cross the partitions and are part of the final chip. Once the partitions are designed and processed individually, they interconnect at the partition boundaries without any extra space by means of interconnect points. Floorplanning in conjunction with partitioning assigns the required amount of space for circuits and wires and places the partitions on chip. Detailed placement, which is controlled by partitioning, also guarantees optimal placement of circuits involved in communicating with the different partitions. Parallel processing (wiring/checking) is in any case possible