Title :
Phony Stability Problem in Fast LDOs
Author :
Stanescu, Cornel
Author_Institution :
Catalyst Semicond. Romania S.R.L., Bucharest
Abstract :
The paper presents a phenomenon associated with the evaluation of fast LDOs. Initial measurements seemed to indicate a potential low phase-margin, which was entirely different from the PSPICE simulations. In fact, it was a phony stability problem given by the response of an input parasitic RLC circuit to the fast-pulsed current load; response that was transmitted to the output through a lower PSRR at high frequency
Keywords :
RLC circuits; SPICE; circuit stability; LDOS; PSPICE simulations; RLC circuit; phony stability problem; Capacitors; Circuit simulation; Circuit stability; DC generators; Feedback circuits; Phase measurement; Pulse circuits; Pulse generation; RLC circuits; SPICE;
Conference_Titel :
International Semiconductor Conference, 2006
Conference_Location :
Sinaia
Print_ISBN :
1-4244-0109-7
DOI :
10.1109/SMICND.2006.284033
