Title :
Splitting of RC-network for accurate model reduction
Author :
Renault, Patricia ; Bazargan-Sabet, Pirouz
Author_Institution :
Univ. Pierre et Marie Curie, Paris, France
Abstract :
Reduction of an extracted RC-network is an important pre-processing step for techniques such as timing and crosstalk noise analysis of VLSI circuit. In a previous paper, we have described a method for reducing an RC-network to a simplified circuit. The experience shows that the accuracy of the method is satisfying but the computation time is not reasonable. In this paper, we propose to split the initial RC-network in order to decrease the computation time.
Keywords :
RC circuits; VLSI; integrated circuit modelling; integrated circuit noise; network analysis; RC network; VLSI circuit; computation time; crosstalk noise analysis; model reduction; timing analysis; Capacitance; Coupling circuits; Crosstalk; Nonlinear equations; Reduced order systems; Time domain analysis; Timing; Very large scale integration; Voltage; Wire;
Conference_Titel :
Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
Print_ISBN :
0-7803-8656-6
DOI :
10.1109/ICM.2004.1434771
