DocumentCode
3258603
Title
A 10-Bit, 40 MSamples/s Low Power Pipeline ADC for System-on-a-Chip Digital TV Application
Author
Francke, Johannes ; Yang, Huazhong ; Luo, Rong
Author_Institution
Dept. of Electron. Eng., Tsinghua Univ., Beijing
Volume
2
fYear
2006
fDate
27-29 Sept. 2006
Firstpage
421
Lastpage
424
Abstract
A 10-bit, 40 Msample/s ADC for a SoC DTV receiver has been designed. Simulations verify that the required dynamic specification of 9.2 effective bits and a spurious free dynamic range (SFDR) higher than 64dB has been reached. Several unconventional techniques have been applied to achieve low power dissipation: Among others, the normally used sample-and-hold stage has been abandoned and the comparators do not exhibit static currents. The ADC core dissipates less than competitive 18mW static power
Keywords
analogue-digital conversion; digital television; low-power electronics; pipeline arithmetic; system-on-chip; 10 bit; 18 mW; comparators; low power pipeline ADC; sample-and-hold stage; spurious free dynamic range; static currents; static power; system-on-a-chip digital TV receiver; CMOS technology; Circuits; Clocks; Delay; Digital TV; Pipelines; Signal design; Signal resolution; System-on-a-chip; Turning;
fLanguage
English
Publisher
ieee
Conference_Titel
International Semiconductor Conference, 2006
Conference_Location
Sinaia
Print_ISBN
1-4244-0109-7
Type
conf
DOI
10.1109/SMICND.2006.284035
Filename
4063263
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