Optimal scheduling and allocation of embedded VLSI chips

A new integer programming (IP) model is presented for synthesizing high speed embedded VLSI chips. A model is presented for simultaneous scheduling, selecting types of functional units, allocation and determining the clock period. Functional units can be chained, multicycled, or pipelined, with different speed and area characteristics. A large number of optimal architectures, satisfying area, speed, and interface constraints, can be synthesized. The synthesis problem is transformed into a tight IP model based on polyhedral theory. A branch and bound algorithm produces globally optimal architectures in practical CPU execution times. It is shown that by simultaneously selecting clock periods and chaining operations, the architectures, synthesized by the optimal architectural synthesis model, are up to 23% faster than previously published architectures. Up to 30 times improvement in CPU execution times is obtained