Title :
Logic BIST for Structured ASIC
Author :
Gavrus, Radu ; Gerigan, Carmen
Author_Institution :
Transilvania Univ., Brasov
Abstract :
The paper presents the design and test methodology for logic BIST implementation based on mucontroller and dedicated logic array-base technology such eASIC. The build in self test (BIST) is a methodology used to decrease manufactory test cost and is the most used form of testing multimillion gates designs or SoC. New testing methodologies are used to reduce the volume of the testing data related with ATE (automatic test equipment). Logic BIST is one of the BIST technique used today for SoC designs to test logic interconnection between logic elements
Keywords :
application specific integrated circuits; automatic test equipment; built-in self test; integrated circuit interconnections; logic gates; logic testing; system-on-chip; SoC testing; automatic test equipment; eASIC; logic array-base technology; logic build in self test; logic elements; logic interconnection testing; manufactory test cost; mucontroller; multimillion gates design testing; Application specific integrated circuits; Automatic test equipment; Automatic testing; Built-in self-test; Costs; Design methodology; Logic arrays; Logic design; Logic testing; Paper technology; ATPG; BIST; SoC; structured ASIC e; ¿Controller;
Conference_Titel :
International Semiconductor Conference, 2006
Conference_Location :
Sinaia
Print_ISBN :
1-4244-0109-7
DOI :
10.1109/SMICND.2006.284039
