HW-SW design methodologies used for a MPEG video compressor synthesis

In the last years many new concepts appeared for the system design, with the so-called HW/SW co-design based on system (SoC) and virtual components. Those concepts rely to methodologies that try to integrate HW and SW design techniques in just one consistent system-level methodology allowing to work in a way that is more secure (specifications and developments are verifiable), more efficient (cost analysable) and can be automated (through systems synthesis). A MPEG demonstrator based on video compression has been designed and validated. It implements video coding using the standard ISO/IEC 13818-2 | ITU-T H.262H (also know as "MPEG2 video"), for the main profile and main level (720×480, 30 fps). The encoder implements frames I or I-pictures. It has been developed a MPEG compressor based on DCT (discrete cosine transform) through two different methodologies. First one, it is based in Matlab DSP builder from Altera that is a down up methodology, based on component instantiation. And the other, it is a top down methodology based on behavioural SystemC description and synthesized with SystemC behavioural compiler from synopsys.