Architecture of a data compression-based low-power scan-path

This paper shows a novel scan-cell architecture that reduces both power consumption and the total consumed energy using a data compression technique. Based on the data compression methodology, the vector set is partitioned into two repeated and unrepeated segments. The repeated part, which is common among some of the vectors, is not changed during the new scan-path where new test vector is filled. This way, every time that a new test vector is applied to the circuit, only the cells of the scan-path which are not repeated are altered and other cells retain their values. This leads to a fewer number of clock cycles when the new test vector is applied to the circuit under test. The architecture proposed in this work has been applied to ISCAS89 circuits. Our simulation results show a reduction in the test power consumption up to about 70% when compared to the conventional scan-path architecture.