Architecture for efficient GALS support in commercial FPGAs

The conflictual demand of faster and larger design on FPGAs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a GALS one with more synchronization constraints. This paper proposes a novel FPGA architecture that is both compatible with existing devices and also can support GALS designs. The main objective was to support synchronous design while providing the basic components required by metastability-free asynchronous communications. We present constraint equations that need to be met in order to avoid synchronization failure. The simulation results show that, with a few additions, a standard FPGA cell is appropriate for GALS methodologies.