Title :
FPGA implementation of constrained LMS algorithm
Author :
Mohanty, Mihir Narayan ; Mishra, Biswajit ; Routray, Aurobinda
Author_Institution :
ITER, Siksha O Anusandhan Univ., Bhubaneswar, India
Abstract :
The use of adaptive systems in a wide variety of applications is one of the factor to update the current research. For building and realizing the adaptive filters, Digital Signal Processors and Application specific Integrated Circuits (ASICs) are the common and popular medium. For such adaptive systems Least Mean Square(LMS) algorithm has occupied an important space for its simplicity and robustness. Practically step size parameter as a constraint, is a key parameter of LMS algorithm. Simultaneously Field Programmable Gate Array (FPGA) has become attractive for the purpose of realization. In this paper, an approach has been proposed to realize the constrained LMS (CLMS) in FPGA Variable step size parameter is considered as the constraint. Simulation results for system identification are provided to support the theoretical analysis. The result shows the efficacy of the approach.
Keywords :
adaptive filters; application specific integrated circuits; digital signal processing chips; field programmable gate arrays; least mean squares methods; ASIC; CLMS; FPGA implementation; FPGA variable step size parameter; adaptive filters; adaptive systems least mean square algorithm; application specific integrated circuits; constrained LMS algorithm; digital signal processors; field programmable gate array; system identification; Adaptive filters; Algorithm design and analysis; Convergence; Field programmable gate arrays; Least squares approximation; Signal processing algorithms; Constrained LMS (CLMS); FPGA; LMS Algorithm; System Identification; Variable Step Size LMS (VSSLMS);
Conference_Titel :
Energy, Automation, and Signal (ICEAS), 2011 International Conference on
Conference_Location :
Bhubaneswar, Odisha
Print_ISBN :
978-1-4673-0137-4
DOI :
10.1109/ICEAS.2011.6147195
