FPGA implementation of constrained LMS algorithm

The use of adaptive systems in a wide variety of applications is one of the factor to update the current research. For building and realizing the adaptive filters, Digital Signal Processors and Application specific Integrated Circuits (ASICs) are the common and popular medium. For such adaptive systems Least Mean Square(LMS) algorithm has occupied an important space for its simplicity and robustness. Practically step size parameter as a constraint, is a key parameter of LMS algorithm. Simultaneously Field Programmable Gate Array (FPGA) has become attractive for the purpose of realization. In this paper, an approach has been proposed to realize the constrained LMS (CLMS) in FPGA Variable step size parameter is considered as the constraint. Simulation results for system identification are provided to support the theoretical analysis. The result shows the efficacy of the approach.