Proceedings. 29th ACM/IEEE Design Automation Conference (Cat. No.92CH3144-3)

The following topics are dealt with: electrical analysis; test generation; two level logic synthesis; field programmable gate array design principles; partitioning and floorplanning; interconnect simulation; scheduling and allocation; concurrent engineering; new approaches to placement; delay-fault testing; synthesis systems and representations; asymptotic waveform evaluation; system-level synthesis; performance issues in logic synthesis; high-level test generation; allocation and binding; design verification and compaction; fault simulation and fault diagnosis; field programmable gate array synthesis; design automation; timing optimization and verification; discrete simulation; multi-level logic synthesis; technology mapping in logic synthesis; frameworks; global issues in routing; path delay analysis; sequential logic synthesis; multilayer channel and over-the-cell routing; automated approaches to formal verification of hardware; advances in high-level synthesis; user perspectives on EDIF/CFI (Electronic Design Interchange Format/CAD Frameworks Initiative); routing for special applications; and issues in analog CAD