A new encoder implementation for low-density parity-check convolutional codes

Low-density parity-check (LDPC) convolutional codes provide an alternative to popular LDPC block codes and are better suited for certain applications such as streaming or packet-based systems with variable frame size. A newly proposed encoder architecture for such codes, referred to as the partial syndrome encoder, is implemented on a Xilinx Virtex II FPGA device in this paper. The results are compared to the existing direct encoder architecture for the same code on the same device. We show that the partial syndrome encoder achieves a better tradeoff between complexity and throughput. Results for larger codes demonstrates that the partial syndrome encoder architecture scales well with the code size.