Title :
High-throughput cost-effective and low-power AES chip design
Author :
Liang, Yunping ; Li, Ye ; Zhang, Chengmin
Author_Institution :
Key Lab. for Biomed. Inf. & Health Eng., Chinese Acad. of Sci., Shenzhen, China
Abstract :
This paper proposes a high-throughput cost-effective and low-power implementation of AES (Advanced Encryption Standard) supporting encryption and decryption with 128-bit cipher key. Considering the cost-effective and low-power, resource-sharing scheme is employed to reduce the hardware complexity of the cipher and decipher. In addition, we adopt composite field arithmetic solution to implement SubByte/InvSubByte and byte-level structure to implement MixColumns/InvMixColumns transformation. Considering the high-throughput, we present a mixed pipelining architecture with both inner-round and outer-round pipelining for 10 iteration rounds of operation. The performance is evaluated on SMIC 0.18 μm CMOS technology and the throughput achieves at 8 Gbps with the cost of only 17519 equivalent NAND2 gates, and the power consumption is only 9.7mw.
Keywords :
CMOS integrated circuits; cryptography; integrated circuit design; low-power electronics; InvMixColumns transformation; MixColumns transformation; NAND2 gates; SMIC CMOS technology; advanced encryption standard; bit rate 8 Gbit/s; byte-level structure; cipher key decryption; hardware complexity; high-throughput cost-effective design; inner-round pipelining; low-power AES chip design; mixed pipelining architecture; outer-round pipelining; power 9.7 mW; resource-sharing scheme; size 0.18 mum; Computer architecture; Encryption; Hardware; Pipeline processing; Power demand; Throughput; Very large scale integration; AES; composite field arithmetic; mixed pipelining; resource-sharing;
Conference_Titel :
Image and Signal Processing (CISP), 2010 3rd International Congress on
Conference_Location :
Yantai
Print_ISBN :
978-1-4244-6513-2
DOI :
10.1109/CISP.2010.5646903
