Knowledge-aware synthesis using hierarchical graph-based sizing and biasing

The hierarchical graph-based sizing and biasing method of analog circuits has been previously developed. Its potential application in the field of knowledge-based analog synthesis is studied. This method reduces the number of optimization variables by taking into account their circuit dependency relations. This is done by automatically generating a design plan to express circuit dependencies. The design plan is then introduced into an optimization loop. The optimization engine uses the Nelder-Mead simplex method. The whole method is successfully applied to a single-ended two-stage amplifier. It produces simulator-like quality designs in a reasonable time, thus allowing interactive design of analog circuits.