Improved hardware accelerated FPGA placement with node swap

Field programmable gate arrays (FPGA) have become solutions of choice for embedded applications with small to medium production numbers. As a result, good CAD tools to support their use are in demand. This paper presents a solution to the FPGA placement problem. Some of the best solutions to date use iterative improvement heuristics such as simulated annealing. However,the run-times of these stochastic solvers becomes unacceptably long for performing placement on large FPGAs. Instead a deterministic iterative solver is proposed that is implemented in hardware. It implements a node-swap heuristic that starts from an initial random placement and iterates until it finds locally optimal solution. Initial results indicate speedups of 3-4 times over software.