Low power 2D DCT chip design for wireless multimedia terminals

Author

Gee Chen, Liang ; Juing-Ying Jiu ; Hao-Chieh Chang ; Pin Lee, Yung ; Wei Ku, Chung

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

4

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

41

Abstract

In this paper, a low power 2-D DCT architecture based on direct 2-D approach is proposed. The direct 2-D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, an adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2-D DCT chip is realized by 0.6 μm single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz

Keywords

SRAM chips; computational complexity; digital signal processing chips; discrete cosine transforms; integrated circuit technology; parallel architectures; read-only storage; 0.6 mum; 100 MHz; 133 MHz; 138 mW; 2D DCT chip design; computational complexity; critical path simulation; discrete cosine transform; maximum input rate; parallel distributed arithmetic architecture; power-saving ROM; sequential access; single-poly double-metal technology; two-port SRAM; wireless multimedia terminals; Adders; Arithmetic; Chip scale packaging; Circuits; Computational complexity; Computer architecture; Discrete cosine transforms; Energy consumption; Read only memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.698747

Filename

698747