Title :
A memory based architecture for real-time convolution with variable kernels
Author :
Moshnyaga, Vasily G. ; Suzuki, Kazuhiro ; Tamaru, Keikichi
Author_Institution :
Dept. of Electron. & Inf. Sci., Fukuoka Univ., Japan
fDate :
31 May-3 Jun 1998
Abstract :
A new architecture for real-time image convolution with variable kernels is proposed. Due to computation flow transformation and memory-logic integration, we were able to exploit the excessive bandwidth inherent in memory and achieve the fine-grain parallelism of computations. Estimations show that the architecture is suitable for a real-time TV and HDTV picture convolution with very large kernels and can be implemented on a single VLSI chip
Keywords :
convolution; high definition television; real-time systems; video signal processing; HDTV; VLSI chip; computation flow transformation; excessive bandwidth; fine-grain parallelism; memory based architecture; memory-logic integration; picture convolution; real-time image convolution; variable kernels; Bandwidth; Computer architecture; Concurrent computing; Convolution; HDTV; Kernel; Memory architecture; Parallel processing; TV; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.698765
