Title :
A new oxide breakdown degradation phenomenon in CMOS transistors
Author :
Yeoh, Teong-San ; Hu, Shze-Jer
Author_Institution :
Intel Technol., Penang, Malaysia
fDate :
27 Nov-1 Dec 1995
Abstract :
The degradation of CMOS inverter circuit performance due to transistor gate oxide breakdown is studied in this paper. This is based on the different gate oxide breakdown sites i.e., gate to drain/source or gate to substrate/well breakdown of p- and n-channel transistors. Gate to drain breakdown of either por n- channel transistor significantly degrades inverter performance
Keywords :
CMOS logic circuits; MOSFET; SPICE; circuit analysis computing; dielectric thin films; electric breakdown; equivalent circuits; logic gates; semiconductor device models; semiconductor device reliability; CMOS inverter circuit performance; CMOS transistors; gate to drain breakdown; lumped element model; n-channel transistors; oxide breakdown degradation phenomenon; p-channel transistors; transistor gate oxide; Breakdown voltage; CMOS technology; Circuit optimization; Circuit simulation; Degradation; Electric breakdown; Inverters; SPICE; Semiconductor process modeling; Trade agreements;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the
Print_ISBN :
0-7803-2797-7
DOI :
10.1109/IPFA.1995.487614
