Title :
Co-synthesis of a configurable SoC platform based on a network on chip architecture
Author :
Véstias, Mário P. ; Neto, Horácio C.
Author_Institution :
INESC-ID, Lisboa
Abstract :
The constant increase of gate capacity and performance of configurable hardware chips made it possible to implement systems-on-chip (SoC) able to tackle the demanding requirements of many embedded systems. In this paper, we propose an approach to the design space exploration of a configurable SoC (CSoC) platform based on a network on chip (NoC) architecture for the execution of dataflow dominated embedded systems. The approach has been validated with the design of a color image compression algorithm in an FPGA
Keywords :
data flow computing; embedded systems; high level synthesis; multiprocessor interconnection networks; network-on-chip; system-on-chip; FPGA; NoC architecture; color image compression algorithm; configurable SoC platform; embedded systems; network on chip architecture; Bandwidth; Computer architecture; Design methodology; Embedded system; Field programmable gate arrays; Hardware; Network topology; Network-on-a-chip; Processor scheduling; Productivity;
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
DOI :
10.1109/ASPDAC.2006.1594644
