VMESS: VLSI mechanical stress simulator

Author

Bhattacharyya, A.B. ; Singh, D.N. ; Metha, R. ; Goswami, I.

Author_Institution

Indian Inst. of Technol., Delhi, India

fYear

1995

fDate

27 Nov-1 Dec 1995

Firstpage

200

Lastpage

205

Abstract

In a systematic study the mechanical stress build up due to the thermal cycling on a silicon wafer with the deposition of overlay films has been modelled taking into account the plasticity introduced in such films when the stress exceeds a critical value. The measurement of mechanical stress in a production CMOS process has been carried out. A VLSI MEchanical Stress Simulator (VMESS) is developed using this integrated model for calculating thermal component of the mechanical stress in a silicon wafer. Using this simulator, it has been shown that the mechanical stress could be engineered at macro level by adjusting the deposition parameters of the films

Keywords

CMOS integrated circuits; VLSI; digital simulation; integrated circuit modelling; integrated circuit reliability; thermal stresses; Si; VLSI; VMESS; deposition parameters; mechanical stress simulator; overlay films; plasticity; production CMOS process; thermal component; thermal cycling; wafer mechanical stress; CMOS process; Mechanical variables measurement; Plastic films; Production; Semiconductor device modeling; Semiconductor films; Silicon; Stress measurement; Thermal stresses; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the

Print_ISBN

0-7803-2797-7

Type

conf

DOI

10.1109/IPFA.1995.487623

Filename

487623