• DocumentCode
    3259909
  • Title

    Crosstalk analysis using reconvergence correlation

  • Author

    Shrivastava, Sachin ; Pratap, Rajendra ; Parameswaran, Harindranath ; Verma, Manuj

  • Author_Institution
    Cadence Design Syst., India Pvt. Ltd., Noida
  • fYear
    2006
  • fDate
    24-27 Jan. 2006
  • Abstract
    In the UDSM era, crosstalk is an area of considerable concern for designers, as it can have a considerable impact on the yield, both in terms of functionality and operating frequency. Methods of crosstalk analysis are pessimistic in nature and the effort is ongoing to come up with techniques that make the analysis as realistic as possible. Using information from timing analysis is one such technique where we use data about overlap in switching among nets to identify those that can potentially switch together. Existing techniques tend to look at the set of a victim and associated aggressor nets in isolation, and select a subset of aggressors based on the absolute timing windows of these nets, thus ignoring the information associated with the fanin of these nets. In reality, however, some of these nets may never switch together because the reconvergence of those nets has not being factored in. Ignoring this correlation can cause false failures being flagged, leading to increased design cycles and conservatism in the design. We propose a technique where the correlation due to reconvergence can be captured in terms of relative switching windows. We apply this technique to real designs and show that this leads to more realistic analysis for crosstalk, and that we can see a reduction in the number of violations reported. We also analyze the effective of the method statistically
  • Keywords
    convergence; correlation methods; crosstalk; network analysis; switching networks; aggressor nets; crosstalk analysis; reconvergence correlation; timing analysis; Application specific integrated circuits; Crosstalk; Delay effects; Failure analysis; Frequency; Information analysis; Noise generators; Performance analysis; Switches; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 2006. Asia and South Pacific Conference on
  • Conference_Location
    Yokohama
  • Print_ISBN
    0-7803-9451-8
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2006.1594649
  • Filename
    1594649