Run-time verification using the VHDL-AMS simulation environment

Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In this paper, we propose a run-time verification approach for VHDL-AMS designs. The essence of this approach is the construction of timed automata from the given specification. Such automata used as monitor, when interfaced with the VHDL-AMS simulator, detect whether the property of interest is violated or satisfied by a simulation trace. For illustration purposes, we applied the approach using VHDL-AMS simulation environment for the verification of a PLL design.