DocumentCode
3259935
Title
Reliability assessment of EPROM memory retention for wafer level sort programming
Author
Yeoh, Teong-San ; Hu, Shze-Jer
Author_Institution
Intel Technol., Penang, Malaysia
fYear
1995
fDate
27 Nov-1 Dec 1995
Firstpage
212
Lastpage
217
Abstract
The feasibility of programming microcontroller EPROM memory in the wafer sort operation instead of the backend test operation is studied. The major concern is EPROM charge loss due to heat treatments during the assembly processing. Theoretical and experimental evaluations as discussed in this paper have shown that wafer level sort programming is a viable option with no impact to quality and reliability
Keywords
EPROM; MOS digital integrated circuits; PLD programming; integrated circuit reliability; microcontrollers; EPROM memory retention; charge loss; heat treatments; reliability assessment; wafer level sort programming; Assembly; Dielectric losses; EPROM; Electrons; Equations; Manufacturing; Microcontrollers; Nonvolatile memory; Read only memory; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the
Print_ISBN
0-7803-2797-7
Type
conf
DOI
10.1109/IPFA.1995.487625
Filename
487625
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