Title :
Pipelined arrays for modular multiplication
Author :
Ciminiera, Luigi
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
fDate :
31 May-3 Jun 1998
Abstract :
New arrays performing the modular multiplication are presented; they operate on a bit-serial basis for both inputs and outputs. The distinctive characteristic of the arrays presented is the possibility to start a new operation, as soon as the cells in the array are no longer used for the previous one, thus allowing bit-level pipelining of the different multiplications. A first array presented has a short clock cycle and long latency, so that it is more suited for applications dealing with long blocks of data to be processed. A second one has a longer clock cycle and shorter latency, and it is more suited for repeated operation on the same block of data
Keywords :
clocks; computational complexity; pipeline arithmetic; bit-serial basis; clock cycle; latency; modular multiplication; pipelined arrays; repeated operation; Circuits; Clocks; Data communication; Delay; Digital arithmetic; Digital signatures; Electronic commerce; Equations; Pipeline processing; Public key cryptography;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.698880
