DocumentCode
326028
Title
A new integrated test structure for on-chip post-irradiation annealing in MOS devices
Author
Chabrerie, C. ; Autran, J.L. ; Flament, O. ; Boudenot, J.C.
Author_Institution
Thomson-CSF, Colombes, France
fYear
1997
fDate
15-19 Sep 1997
Firstpage
228
Lastpage
233
Abstract
We have developed a prototype test structure (named THERMOS) demonstrating the feasibility and the interest of the on-chip heating in a Silicon-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip annealing of irradiated n-channel transistors
Keywords
MOSFET; annealing; radiation hardening (electronics); semiconductor device testing; silicon-on-insulator; CMOS SOI technology; THERMOS; integrated test structure; n-channel MOS transistor; on-chip post-irradiation annealing; radiation hardening; Annealing; Circuit testing; Heating; MOS devices; MOSFETs; Packaging; Resistors; Silicon; Temperature; Thermal conductivity;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation and Its Effects on Components and Systems, 1997. RADECS 97. Fourth European Conference on
Conference_Location
Cannes
Print_ISBN
0-7803-4071-X
Type
conf
DOI
10.1109/RADECS.1997.698896
Filename
698896
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