Adaptive FEC on a reconfigurable processor for wireless multimedia communications

Due to variations in environmental conditions, many computationally intensive algorithms that need to be processed in a compact form factor often require a more flexible solution than a specialized ASIC. A ReConfigurable Processor Board (RCP) was jointly developed by a University of California San Diego and L3 Communications Corporation for implementing Digital Signal Processing (DSP) algorithms for wireless multimedia communications. The flexible architecture of the RCP makes it ideal for performing parallel tasks and can process multiple algorithms concurrently. As an application example, an Adaptive Viterbi Decoder (AVD) was designed and implemented on the RCP. The AVD can adapt itself to varying channel characteristics and service requirements at run time. It is capable of processing data with constraint lengths from 7 to 15 and code rates form 1/2 to 1/6. The AVD provides robust decoding for video, audio and data communication channels