Pipelined TSPC barrel shifter with scan test facilities for VLSI implementation of high speed DSP applications

Author

Pereira, R. ; Michell, J.A. ; Solana, J.M.

Author_Institution

Dept. de Electronica, Cantabria Univ., Santander, Spain

fYear

1992

fDate

1-5 Jun 1992

Firstpage

405

Lastpage

406

Abstract

A barrel shifter for high speed data processing is described, together with the test-oriented structure which it has been provided with. The circuit has a pipeline architecture and has been designed using the TSPC strategy, which has allowed the achievement of a high operation rate. Its implementation has been carried out in full-custom style with 1.5 μm CMOS technology. The incorporated test-oriented structure allows serial acquisition of output data using the normal mode instruction register

Keywords

CMOS integrated circuits; VLSI; boundary scan testing; built-in self test; digital signal processing chips; integrated circuit testing; logic testing; pipeline processing; 1.5 micron; CMOS technology; TSPC strategy; VLSI; barrel shifter; full-custom style; high speed DSP applications; high speed data processing; normal mode instruction register; pipeline architecture; scan test facilities; test-oriented structure; CMOS technology; Circuit testing; Clocks; Digital signal processing; Frequency; Logic devices; Logic testing; Pipelines; Test facilities; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '92, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-2845-6

Type

conf

DOI

10.1109/EUASIC.1992.227990

Filename

227990